Modern semiconductor technology is pursuing new approaches for improving the performance of field-effect transistors. These approaches consist not only in continued scaling and miniaturization of the field-effect transistors, but also in the development of new types of transistors.
These new types of transistors include, for example, fin field-effect transistors, in which the channel region between two source/drain regions is realized in a semiconductor fin, above which a gate region is deposited.
Another new type of transistor is what is known as the dual gate transistor. In a dual gate field-effect transistor, unlike in conventional field-effect transistors, the channel region is driven not just from one side, but rather, in a sandwich design, a thin channel region is driven from both sides, i.e. for example from above and below, by means of a gate electrode in each case, so that the electrical conductivity of the channel region can be particularly well controlled. However, the dual gate transistor technology imposes high demands on the process engineering used.
One of the main problems in the production of a planar dual gate field-effect transistor is the orientation of the top gate electrode and of the bottom gate electrode with respect to one another. With electron beam lithography, the two gate regions can be aligned with an accuracy of at best 10 nm with respect to one another. In other words, the process engineering used results in a lateral offset between the two gate electrodes of at least 10 nm. However, dual gate field-effect transistors are of interest in particular for feature sizes in the range from typically 20 nm to 10 nm. Therefore, accurate alignment of top gate and bottom gate relative to one another is very important for the functioning of a dual gate field-effect transistor.
Another obstacle to the production of planar dual gate MOS field-effect transistors is the highly complex production steps and the expensive installations which are required for the production of a dual gate field-effect transistor.
One way of producing dual gate field-effect transistors in accordance with the prior art consists in using what is known as an SOI (silicon-on-insulator) substrate, i.e. a substrate in which a silicon oxide layer is formed on a silicon bulk wafer, and a thin top silicon layer is formed on the silicon oxide layer. The top silicon layer is very thin and can be used as the channel region of a dual gate field-effect transistor, since a channel region of this type should be sufficiently thin to allow it to be driven successfully from both sides.
To summarize, processes for the production of layer arrangements which can be used as dual gate field-effect transistor arrangements which are known from the prior art are very expensive and complex to realize. This applies in particular to dual gate field-effect transistors produced using SOI technology.
“Silicon Wafer Bonding Technology for VLSI and MEMS applications”, Iyer, S S, Auberton-Herve, A J (eds.), Inspect IEE, 2002, discloses fundamental principles of silicon wafer bonding technology.
Tserepi, A, Tamis, C, Gogolides, E, Nassipoulou, A G, (2003) PhysStatSol A 197, 163, discloses a process for etching porous silicon.
Lehmann, Volker, “Electrochemistry of Silicon”, chapter 6, Wiley-VCH-Verlag, 2002, discloses a process for forming porous silicon.
DE 102 23 719 C1 discloses a layer arrangement, a process for producing a layer arrangement and a silicon-on-insulator wafer arrangement. The layer arrangement includes a first substrate having a first main surface, which includes a first delamination layer that can be removed by means of heat treatment. Furthermore, the layer arrangement has a second substrate with a second main surface, which includes a temperature-stable, second removable delamination layer. The first main surface of the first substrate is secured to the second main surface of the second substrate.
DE 102 23 709 A1 discloses a process for producing a dual gate field-effect transistor. The process includes the following steps: forming a first gate region on a silicon-on-insulator substrate of a first wafer, forming a layer with a planar surface over the silicon-on-insulator substrate and the first gate region, bonding a second wafer onto the planar surface of the first wafer and forming a second gate region, opposite the first gate region, in the silicon-on-insulator substrate.